AGGA4GNSS

Demonstration of the AGGA-4 IP Core on a GNSS Receiver Breadboard

Aims

• Demonstration of the AGGA-4 IP Core as a viable alternative to the AGGA-4 ASIC for GNSS receivers
• Integration of the IP Core into a state-of-the-art FPGA-based SDR hardware platform
• Verification of functionality, performance, and correctness of the receiver implementation
• Characterization of receiver performance (e.g., acquisition, tracking, PVT)
• Delivery of a TRL 4 GNSS receiver breadboard as proof of concept
• Recommendations for future design evolutions toward commercial receivers, with a focus on small satellites

Brief Description

The AGGA-4 ASIC, developed in 2014 and manufactured by Microchip (FR), is a well-established space-qualified building part for high reliability high performance GNSS receivers. A large number of GNSS receivers for EO applications are using this ASIC operationally, including some Proba missions.
Building on the heritage of the AGGA-4 ASIC, the project work is to develop a configurable AGGA-4 IP Core for modern FPGAs, enabling greater flexibility and integration into satellite avionics. This activity will demonstrate the IP Core in a realistic GNSS receiver, replacing non-core functions with modern alternatives. The work includes hardware/software integration, verification, and performance testing using representative GNSS signals. The outcome will validate the AGGA-4 IP Core’s suitability for future GNSS receivers in both flagship missions and NewSpace.